Phase-locked loops (PLLs) have been widely used in high-speed communication systems because PLLs efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL, this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency. The prior art has described ways of selecting operating points of voltage and frequency statically, for example, stopping execution while allowing the PLL to frequency lock to a new frequency. This slows system operations and complicates system design.
One of the key circuits in a PLL is a voltage-controlled oscillator (VCO). Circuits in the PLL generate an error voltage that is coupled to the VCO to control the frequency of the VCO output. By frequency dividing the output of the PLL and feeding it back and comparing it to a low frequency crystal-controlled reference clock, a stable high frequency clock may be generated. The VCO in a PLL typically has a range over which the frequency of the VCO may be voltage-controlled. In systems employing frequency scaling, it is desirable to have a voltage-controlled frequency range for normal voltage operation and another voltage-controlled frequency range for low voltage operation without resorting to two VCOs.
The VCO circuit is sometimes considered the most difficult circuit to implement in the PLL especially if ultra high frequencies and low jitter are required. Typically, the VCO is made using five or more inverting elements in a ring oscillator configuration. Standard ring oscillator topologies are relatively simple to design, have low-power, and have robust noise margins. The main drawback to the ring oscillator is that many stages are required to generate high quality signals and many stages lead to lower frequencies.
The requirements for high frequency VCOs are becoming more demanding and in some cases the shortest ring oscillator of three stages may not produce sufficiently high frequencies. A number of circuit topologies have been developed to improve the frequencies possible with the ring oscillator. One such circuit topology is the “classic interpolator” as seen in FIG. 1. Another circuit topology is the “phased oscillator” design shown in FIG. 2. Both of these circuit topologies provide a frequency boost to the standard ring oscillator but both are limited to five or more oscillator stages. In most cases, these oscillator circuit topologies produce frequencies in the range of a standard three stage ring oscillator. Another drawback to these two oscillator circuit topologies is the lack of a complementary output. When clock frequencies become very high, it becomes more difficult to generate complementary signals that are non-skewed.
Therefore, there is a need for a way of configuring a ring oscillator with an odd number of stages of as few as three having voltage controlled frequency capabilities and producing complementary non-skewed signals with symmetrical duty cycles and high signal quality.